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Hardware-Verilog-Parser-0.11
River stage zero No dependents

Changes for version 0.11

  • fixed a bunch of warning messages about unintialized data. ran a bunch of extreme verilog files through the parser. fixed a bunch of errors in the grammar rules. tried to clean up some of the grammar rules to run a bit faster. fixed a number of StdLogic.pm bugs to perform math correctly.

Modules

Hardware::Verilog::Parser
A complete grammar for parsing Verilog code using perl

Provides

Hardware::Verilog::Hierarchy
in Hierarchy.pm
Hardware::Verilog::StdLogic
in StdLogic.pm

Other files